Nanowire Integration and Up-scaling

Nanowires allow researchers to carry out beautiful physics experiments [26] and may also have great potential for both future device applications and novel device architectures [27]. From an implementation point of view, however, it would be naïve to assume that nanowires will suddenly replace CMOS technology. Instead, we can expect that nanowire technology will gradually find its place by adding functionality, offering process advantages, and delivering superior performance in selected areas. This will be driven by advantages such as the potential for wrap gates, three-dimensional integration, and the ability to grow heterostructures of materials with a large lattice mismatch. It is of vital importance to carefully investigate this potential. Moreover, in comparison to other ‘nanotechnology’ device options, semiconductor nanowires may have the potential to be implemented on an existing semiconductor infrastructure and can thus benefit from continuous improvements in CMOS technology. This scenario, however, needs on-going innovations and breakthroughs, and there is no doubt that there are further challenges to overcome before nanowires are implemented in a high-end product. A few of the main challenges are briefly discussed below.   Compatibility with manufacturing   Contamination issues are a major source of concern when considering implementation of new processes in an actual production line. However, many new materials have been introduced in recent years in light of physical limitations faced by the more traditional materials used in the microelectronics industry for decades (Si, SiO2, polycrystalline Si). For instance in FEOL, HfO2 and other ‘nonstandard’ high dielectric constant materials are used as replacements for SiO2 as the gate dielectric. At the contact level, Ti, Ni, and Ni/Pt self-aligned silicides have gradually replaced Co as the material of choice. Also, in BEOL, the transition from Al and SiO2 to Cu and so-called low-k dielectrics has helped to pave the road for the acceptance of many more exotic materials. It is critical for this last implementation that a diffusion barrier material can be reliably placed between the interconnect metal and Si, because some metals (such as Cu and Au) create deep trap levels in the Si bandgap and thus cause undesirable changes to the electrical properties of Si. Also, as contamination resulting from process errors is unavoidable, cleaning solutions need to be available for encapsulation and effective removal of any material used in production. This last requirement is the main differentiator between the now widely accepted use of Cu as the interconnect metal of choice and the continuing strong resistance against the use of Au. Today, Au is the most common material used for particle-assisted nanowire growth, as discussed in the first section. However, Au has the disadvantage of being difficult to remove/clean and therefore other, CMOS-compatible catalysts are being considered.   Wire growth and thermal budget   The thermal budget available for nanowire growth limits the materials that can be used. Clearly, this boundary condition and the contamination issues mentioned above depend on where in the process implementation is to be considered. In FEOL, high temperatures are used for dopant activation (flash anneal to 1100 ºC), while the replacement of Co by nickel silicide limits subsequent process temperatures to below 450 ºC for stability reasons. Low-k materials used in BEOL typically become unstable between 400 ºC and 450 ºC. This clearly limits the maximum temperature for growth of nanowires intended to bring additional functionality to existing CMOS. However, nanowire growth has been reported at consistently lower temperatures, which indicates that implementation may be possible within the thermal constraints of the process.
Device fabrication and variability Once good control over wire growth has been achieved, further processing is required to integrate nanowires into a functional device.  However, to make a nanowire transistor with stable and reproducible electrical characteristics, several critical issues needto be addressed, as shown in Fig. 10.
Firstly, the length and diameter of the wire need to be controlled within tight limits. After growth, the wire surface needs to be properly passivated by thermal oxidation or conformal atomic layer deposition of a high-k material serving as gate dielectric. Next, the formation of a gate with an accurately controlled length needs to be accomplished. As impurity doping is no longer effective in ultrathin body devices, the threshold voltage of the transistor needs to be set by the gate material with an appropriate work function. This issue is, however, not specific to nanowire technology and breakthroughs in scaled CMOS will help.
	Figure 10. Schematic cross section of a vertical nanowire transistor; critical areas are indicated.
Source and drain regions are created by conventional impurity doping or, alternatively, by metallization to form so-called Schottky barrier transistors. In general, the overlap region of gate to source and drain must be optimized for high performance and an unwanted voltage drop has to be reduced to a minimum, i.e., the source and the drain region have to have Ohmic contacts to the metal wiring (this has in fact recently been achieved with silicide contacts [28]).  As a result of the extremely small contact and current-carrying area, parasitic series resistance is believed to be critical in a nanowire transistor, again very similar to scaled CMOS. The mechanical properties of nanowires also need to be investigated in order to determine how well they withstand such process steps as spin-on of dielectric materials and mechanical polishing.However, the first realizations of vertical nanowire FETs look very encouraging [18,23,25].
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