Doping and Si Integration

Doping   One of the main reasons for the usefulness of semiconductors in electronics is the possibility of controlling the conductivity and carrier type by adding impurities. In this way, a semiconductor can be ‘doped’ to conduct with negative electrons (n-type) or positive holes (p-type), enabling p–n junctions and transistors to be formed. This is also a key advantage of semiconductor nanowires over carbon nanotubes – the major competitor in the field of one-dimensional electronics – for which the band gap and doping are hard to control. However, it is not yet fully understood how dopants are incorporated in particle-assisted growth of nanowires, and how the presence of dopants affects wire growth. Many growth techniques use carbon-containing precursor materials, which may under some conditions introduce unintentional carbon impurities into the nanowire. It is therefore necessary to understand how, and under which conditions, impurities incorporate into nanowires. Another intriguing problem associated with the doping of nanometer-scale structures relates to statistics: a doping level of 1018 cm-3 in a 5 nm thick Si wire correlates to only one dopant every 50 nm of wire. Hence, a short gate-length transistor of, say, 30 nm gate length will either be empty of dopants or have one dopant atom in the active transistor region. For this reason, it seems clear that one may choose to design a technology to operate without impurity dopants in the active device volume.

Si Integration   Integration on Si is essential for nanowires to be of interest for large scale electronic applications. Further details of this will be discussed in a later section; however, it does present a few specific challenges for nanowire growth. The most significant is probably the elimination of Au from the process. Since Au has to be avoided in CMOS, compatible catalysts or catalyst-free growth techniques must be developed. The difficulty here is that, while many other metals have been studied for use as collector particles and a few have indicated promise [14], the crystal quality, reproducibility, and direction control achievable using Au have not been demonstrated with any other metal. It may turn out that particle-free techniques provide the best solution to this problem. For this to be the case, better length and diameter control must be developed. It is also necessary to find processing conditions that either favor or force growth of nanowires in certain crystal directions, preferably the [001] direction. Such ‘forced’ growth of InP nanowires in the [001] direction on InP substrates has been demonstrated [15]; it will be of interest to develop similar results on Si substrates. Growth temperatures will also be restricted, depending on whether growth occurs at the front-end-of-line (FEOL) or back-end-of-line (BEOL) of CMOS.

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