Nanowire Devices

Electronic devices form the basic constituents of modern integrated circuits. They come in many varieties and are used to amplify and rectify electronic signals, perform logic operations, or store charge in digital memories. Next to these purely electronic functions, other devices interact with light, heat flow, or even biological fluids. The small size and unprecedented capability of combining semiconductors with widely differing lattice parameters [12,21] offer exciting new possibilities for devices. Nanowire device researchers face the exciting challenge of deciding which devices, and thus which future applications, are particularly promising for this new class of material.
Field-effect transistors    Amongthe many possibilities, the FET stands out as being the modernworkhorse of the semiconductor industry. Therefore, it is notsurprising that most efforts on nanowire devices have focused on makingnanowire FETs. Researchers have typically either studied individual nanowires [22] randomly placed on a substrate (which frequently also functions as the gate electrode), or have tried to fabricate transistors from arrays of vertical nanowires. Although the latter approach is much more complex in terms of device fabrication, it has the advantage of studying a large number of wires and hence taking full account of the expected statistical device fluctuations from the start. European research groups have made significant contributions in this area including wrap-gated Si [23] and InAs nanowires [24], even incorporating first attempts at bandgap engineering into the channel of the device.This work, together with similar research from the U.S. [25], has shown that Si nanowires can deliver drive currents comparable to standard Si devices, and that bandgap engineering of the nanowire channel adds a completely new degree of freedom in tuning the device performance of the FET. These are important milestones in nanowire device research. Especially in devices with a controlled number of wires per electrode, the characterization of nanowire devices can be taken to a level more comparable to the industry standard. Besides FETs, there are other natural device candidates for nanowires. One example is a high-performance radio-frequency transistor, illustrated in Fig. 9. Such a device could be used in future mobile phones or other communication devices. Initial modeling of a nanowire device indicates a particularly promising combination of high speed and high breakdown voltages. Experimental work to confirm these predictions is on-going.      Device characterization and optimization One handicap that nanowire device researchers face is the absence ofeasy capacitance-based characterization tools. This is primarilybecause of the small amount of charge involved in nanowire deviceoperation, which is well below today’s standard measurement techniques.
	Figure 9. A possible nanowire junction transistor. (a) Sketch of the device geometry. (b) Potential distribution in a Si nanowire junction. The depletion zone is indicated in gray. (c) Simulated breakdown voltage of a nanowire-substrate junction in Si.
Throughout the history of semiconductor devices, capacitance voltage measurements on large-area structures have been essential for determining the quality of contacts, heterojunctions, dopant incorporation, and metal-oxide-semiconductor sandwiches. For nanowire devices, a large and controlled number of devices must typically be connected in parallel, and ‘parasitic’ capacitances arising from the environment must be carefully minimized to be smaller than those of the active devices. In practice, this amounts to solving the nanowire integration and up-scaling problem first – a huge challenge in itself, as will be discussed in the next section. Instead, nanowire device characterization typically relies only on current-voltage measurements on a small number of devices. An innovation in this area, such as a special device geometry or measurement technique, could significantly accelerate the development of new devices. While research at the individual device level is beginning to produce interesting experimental results, an important aspect is awareness of the intimate link between device performance and the way the devices are assembled or integrated to make any functional unit in future circuits. While it was possible to separate the devices from their environment in the past, this is no longer true in modern integrated circuits, which are increasingly dominated by the capacitances and resistances of the connecting elements rather than the devices themselves. The need for minimizing these parasitic elements will be touched upon in the next section concerning nanowire device integration.
Continue